Earlier this week, Nvidia surprise-announced their new Vera Rubin structure (no relation to the not too long ago unveiled telescope) on the Consumer Electronics Show in Las Vegas. The brand new platform, set to succeed in clients later this 12 months, is marketed to supply a ten-fold discount in inference prices and a four-fold discount in what number of GPUs it might take to coach sure fashions, as in comparison with Nvidia’s Blackwell structure.
The same old suspect for improved efficiency is the GPU. Certainly, the brand new Rubin GPU boasts 50 quadrillion floating-point operations per second (petaFLOPS) of 4-bit computation, as in comparison with 10 petaflops on Blackwell, not less than for transformer-based inference workloads like large language models.
Nonetheless, specializing in simply the GPU misses the larger image. There are a complete of six new chips within the Vera-Rubin-based computer systems: the Vera CPU, the Rubin GPU, and 4 distinct networking chips. To realize efficiency benefits, the parts should work in live performance, says Gilad Shainer, senior vice chairman of networking at Nvidia.
“The identical unit related otherwise will ship a very completely different stage of efficiency,” Shainer says. “That’s why we name it excessive co-design.”
Expanded “in-network compute”
AI workloads, each coaching and inference, run on giant numbers of GPUs concurrently. “Two years again, inferencing was primarily run on a single GPU, a single field, a single server,” Shainer says. “Proper now, inferencing is turning into distributed, and it’s not simply in a rack. It’s going to go throughout racks.”
To accommodate these vastly distributed duties, as many GPUs as doable must successfully work as one. That is the intention of the so-called scale-up network: the connection of GPUs inside a single rack. Nvidia handles this reference to their NVLink networking chip. The brand new line consists of the NVLink6 change, with double the bandwidth of the previous version (3,600 gigabytes per second for GPU-to-GPU connections, as compared to 1,800 GB/s for NVLink5 switch).
In addition to the bandwidth doubling, the scale-up chips also include double the number of SerDes—serializer/deserializers (which allow data to be sent across fewer wires) and an expanded number of calculations that can be done within the network.
“The scale-up network is not really the network itself,” Shainer says. “It’s computing infrastructure, and some of the computing operations are done on the network…on the switch.”
The rationale for offloading some operations from the GPUs to the network is two-fold. First, it allows some tasks to only be done once, rather than having every GPU having to perform them. A common example of this is the all-reduce operation in AI training. During training, each GPU computes a mathematical operation called a gradient on its own batch of data. In order to train the model correctly , all the GPUs need to know the average gradient computed across all batches. Rather than each GPU sending its gradient to every other GPU, and every one of them computing the average, it saves computational time and power for that operation to only happen once, within the network.
A second rationale is to hide the time it takes to shuttle knowledge in-between GPUs by doing computations on them en-route. Shainer explains this by way of an analogy of a pizza parlor attempting to hurry up the time it takes to ship an order. “What are you able to do should you had extra ovens or extra employees? It doesn’t enable you; you can also make extra pizzas, however the time for a single pizza goes to remain the identical. Alternatively, should you would take the oven and put it in a automotive, so I’m going to bake the pizza whereas touring to you, that is the place I save time. That is what we do.”
In-network computing will not be new to this iteration of Nvidia’s structure. The truth is, it has been in frequent use since round 2016. However, this iteration provides a broader swath of computations that may be carried out throughout the community to accommodate completely different workloads and completely different numerical codecs, Shainer says.
Scaling out and throughout
The remainder of the networking chips included within the Rubin structure comprise the so-called scale-out community. That is the half that connects completely different racks to one another throughout the knowledge middle.
These chips are the ConnectX-9, a networking interface card; the BlueField-4 a so-called knowledge processing unit, which is paired with two Vera CPUs and a ConnectX-9 card for offloading networking, storage, and safety duties; and at last the Spectrum-6 Ethernet change, which makes use of co-packaged optics to ship knowledge between racks. The Ethernet change additionally doubles the bandwidth of the earlier generations, whereas minimizing jitter—the variation in arrival occasions of knowledge packets.
“Scale-out infrastructure must guarantee that these GPUs can talk nicely to be able to run a distributed computing workload and which means I would like a community that has no jitter in it,” he says. The presence of jitter implies that if completely different racks are doing completely different elements of the calculation, the reply from every will arrive at completely different occasions. One rack will all the time be slower than the remainder, and the remainder of the racks, stuffed with expensive gear, sit idle whereas ready for that final packet. “Jitter means dropping cash,” Shainer says.
None of Nvidia’s host of latest chips are particularly devoted to attach between data centers, termed ‘“scale-across.” However Shainer argues that is the subsequent frontier. “It doesn’t cease right here, as a result of we’re seeing the calls for to extend the variety of GPUs in a knowledge middle,” he says. “100,000 GPUs will not be sufficient anymore for some workloads, and now we have to join a number of knowledge facilities collectively.”
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