For prime-performance chips in large data centers, math might be the enemy. Because of the sheer scale of calculations occurring in hyperscale data centers, working around the clock with tens of millions of nodes and huge quantities of silicon, extraordinarily unusual errors seem. It’s merely statistics. These uncommon, “silent” knowledge errors don’t present up throughout typical quality-control screenings—even when corporations spend hours on the lookout for them.
This month on the IEEE International Reliability Physics Symposium in Monterey, Calif., Intel engineers described a way that uses reinforcement learning to uncover extra silent knowledge errors sooner. The corporate is utilizing the machine learning methodology to make sure the standard of its Xeon processors.
When an error occurs in a knowledge heart, operators can both take a node down and change it, or use the flawed system for lower-stakes computing, says Manu Shamsa, {an electrical} engineer at Intel’s Chandler, Ariz., campus. However it could be a lot better if errors may very well be detected earlier on. Ideally they’d be caught earlier than a chip is included in a pc system, when it’s attainable to make design or manufacturing corrections to stop errors recurring sooner or later.
“In a laptop computer, you gained’t discover any errors. In knowledge facilities, with actually dense nodes, there are excessive probabilities the celebrities will align and an error will happen.” —Manu Shamsa, Intel
Discovering these flaws just isn’t really easy. Shamsa says engineers have been so baffled by them they joked that they should be as a consequence of spooky motion at a distance, Einstein’s phrase for quantum entanglement. However there’s nothing spooky about them, and Shamsa has spent years characterizing them. In a paper introduced on the similar convention final yr, his workforce gives an entire catalog of the causes of those errors. Most are as a consequence of infinitesimal variations in manufacturing.
Even when every of the billions of transistors on every chip is useful, they don’t seem to be utterly an identical to at least one one other. Delicate variations in how a given transistor responds to modifications in temperature, voltage, or frequency, for example, can result in an error.
These subtleties are more likely to crop up in large knowledge facilities due to the tempo of computing and the huge quantity of silicon concerned. “In a laptop computer, you gained’t discover any errors. In knowledge facilities, with actually dense nodes, there are excessive probabilities the celebrities will align and an error will happen,” Shamsa says.
Some errors might crop up solely after a chip has been put in in a knowledge heart and has been working for months. Small variations within the properties of transistors may cause them to degrade over time. One such silent error Shamsa has discovered is said to electrical resistance. A transistor that operates correctly at first, and passes commonplace assessments to search for shorts, can, with use, degrade in order that it turns into extra resistant.
“You’re considering every thing is ok, however beneath, an error is inflicting a unsuitable determination,” Shamsa says. Over time, due to a slight weak spot in a single transistor, “one plus one goes to a few, silently, till you see the impression,” Shamsa says.
The brand new method builds on an current set of strategies for detecting silent errors, known as Eigen tests. These assessments make the chip do arduous math issues, repeatedly over a time frame, within the hopes of constructing silent errors obvious. They contain operations on completely different sizes of matrices full of random knowledge.
There are a lot of Eigen assessments. Working all of them would take an impractical period of time, so chipmakers use a randomized method to generate a manageable set of them. This protects time however leaves errors undetected. “There’s no precept to information the choice of inputs,” Shamsa says. He needed to discover a solution to information the choice so {that a} comparatively small variety of assessments might flip up extra errors.
The Intel workforce used reinforcement learning to develop assessments for the a part of its Xeon CPU chip that performs matrix multiplication utilizing what are known as fuse-multiply-add (FMA) directions. Shamsa says they selected the FMA area as a result of it takes up a comparatively massive space of the chip, making it extra susceptible to potential silent errors—extra silicon, extra issues. What’s extra, flaws on this a part of a chip can generate electromagnetic fields that have an effect on different elements of the system. And since the FMA is turned off to avoid wasting energy when it’s not in use, testing it entails repeatedly powering it up and down, doubtlessly activating hidden defects that in any other case wouldn’t seem in commonplace assessments.
Throughout every step of its coaching, the reinforcement-learning program selects completely different assessments for the doubtless faulty chip. Every error it detects is handled as a reward, and over time the agent learns to pick out which assessments maximize the probabilities of detecting errors. After about 500 testing cycles, the algorithm discovered which set of Eigen assessments optimized the error-detection price for the FMA area.
Shamsa says this system is 5 occasions as more likely to detect a defect as randomized Eigen testing. Eigen assessments are open source, a part of the openDCDiag for knowledge facilities. So different customers ought to be capable to use reinforcement studying to switch these assessments for their very own programs, he says.
To a sure extent, silent, refined flaws are an unavoidable a part of the manufacturing course of—absolute perfection and uniformity stay out of attain. However Shamsa says Intel is making an attempt to make use of this analysis to study to search out the precursors that result in silent knowledge errors sooner. He’s investigating whether or not there are pink flags that might present an early warning of future errors, and whether or not it’s attainable to vary chip recipes or designs to handle them.
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