This week on the IEEE Electronic Components and Packaging Technology Conference, Intel unveiled that it’s creating new chip packaging know-how that may enable for larger processors for AI.
With Moore’s Regulation slowing down, makers of superior GPUs and different knowledge heart chips are having so as to add extra silicon space to their merchandise to maintain up with the relentless rise of AI’s computing wants. However the most measurement of a single silicon chip is fastened at round 800 sq. millimeters (with one exception), so that they’ve needed to flip to advanced packaging technologies that combine a number of items of silicon in a manner that lets them act like a single chip.
Three of the improvements Intel unveiled at ECTC have been geared toward tackling limitations in simply how a lot silicon you possibly can squeeze right into a single bundle and the way huge that bundle may be. They embrace enhancements to the know-how Intel makes use of to hyperlink adjoining silicon dies collectively, a extra correct technique for bonding silicon to the bundle substrate, and system to increase the dimensions of a vital a part of the bundle that take away warmth. Collectively, the applied sciences allow the mixing of greater than 10,000 sq. millimeters of silicon inside a bundle that may be larger than 21,000 mm2—an enormous space concerning the measurement of 4 and a half credit cards.
EMIB will get a 3D improve
One of many limitations on how a lot silicon can slot in a single bundle has to do with connecting numerous silicon dies at their edges. Utilizing an natural polymer bundle substrate to interconnect the silicon dies is essentially the most reasonably priced choice, however a silicon substrate lets you make extra dense connections at these edges.
Intel’s resolution, launched greater than 5 years in the past, is to embed a small sliver of silicon within the natural bundle beneath the adjoining edges of the silicon dies. That sliver of silicon, referred to as EMIB, is etched with high-quality interconnects that enhance the density of connections past what the natural substrate can deal with.
At ECTC, Intel unveiled the newest twist on the EMIB know-how, referred to as EMIB-T. Along with the same old high-quality horizontal interconnects, EMIB-T gives comparatively thick vertical copper connections referred to as through-silicon vias, or TSVs. The TSVs enable energy from the circuit-board beneath to straight connect with the chips above as a substitute of getting to route across the EMIB, decreasing energy misplaced by an extended journey. Moreover, EMIB-T incorporates a copper grid that acts as a floor airplane to cut back noise within the energy delivered resulting from course of cores and different circuits all of the sudden ramping up their workloads.
“It sounds easy, however this can be a know-how that brings quite a lot of functionality to us,” says Rahul Manepalli, vice chairman of substrate packaging know-how at Intel. With it and the opposite applied sciences Intel described, a buyer might join silicon equal to greater than 12 full measurement silicon dies—10,000 sq. millimeters of silicon—in a single bundle utilizing 38 or extra EMIB-T bridges.
Thermal management
One other know-how Intel reported at ECTC that helps enhance the dimensions of packages is low-thermal-gradient thermal compression bonding. It’s a variant of the know-how used as we speak to connect silicon dies to natural substrates. Micrometer-scale bumps of solder are positioned on the substrate the place they are going to connect with a silicon die. The die is then heated and pressed onto the microbumps, melting them and connecting the bundle’s interconnects to the silicon’s.
As a result of the silicon and the substrate increase at totally different charges when heated, engineers should restrict the inter-bump distance, or pitch. Moreover, the enlargement distinction makes it troublesome to reliably make very massive substrates stuffed with numerous silicon dies, which is the course AI processors have to go.
The brand new Intel tech makes the thermal enlargement mismatch extra predictable and manageable, says Manepalli. The result’s that very-large substrates may be populated with dies. Alternatively, the identical know-how can be utilized to extend the density of connections to EMIB all the way down to about one each 25 micrometers.
A flatter warmth spreader
These larger silicon assemblages will generate much more warmth than as we speak’s techniques. So it’s vital that the warmth’s pathway out of the silicon isn’t obstructed. An built-in piece of metallic referred to as a warmth spreader is vital to that, however making one large enough for these massive packages is troublesome. The bundle substrate can warp and the metallic warmth spreader itself won’t keep completely flat; so it won’t contact the tops of the new dies it’s presupposed to be sucking the warmth from. Intel’s resolution was to assemble the built-in warmth spreader in elements as a substitute of as one piece. This allowed it so as to add further stiffening elements amongst different issues to maintain every thing in flat and in place.
“Preserving it flat at greater temperatures is an enormous profit for reliability and yield,” says Manepalli.
Intel says the applied sciences are nonetheless within the in R&D stage and wouldn’t touch upon when these applied sciences would debut commercially. Nonetheless, they are going to probably should arrive within the subsequent few years for the Intel Foundry to compete with TSMC’s planned packaging expansion.
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